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The 3rd IEEE International Workshop on System-on-Chip for Real-Time Applications (IWSOC'03)
Optimized Datapath Design by Evolutionary Computation
Calgary, Alberta, Canada
June 30-July 02
ISBN: 0-7695-1944-X
S. G. Ara?, Electrical Engineering Dept. - UFRJ
A. C. Mesquita, Electrical Engineering Dept. - UFRJ
A. C. P. Pedroza, Electrical Engineering Dept. - UFRJ
High-level design entry tools offer a nice framework to deal with today?s complex systems while shortening the design cycle. Nevertheless, such tools provide poor quality results both in area usage and timing performance issues. This paper presents a methodology to design optimized datapaths based on evolutionary techniques and HLS tools. VHDL descriptions of the system are automatically generated by Genetic Programming. To improve the design structural quality of such descriptions a two-stage, multiobjective optimization algorithm is used to insure both desired functionality and area constraints.
Citation:
S. G. Ara?, A. C. Mesquita, A. C. P. Pedroza, "Optimized Datapath Design by Evolutionary Computation," iwsoc, pp.6, The 3rd IEEE International Workshop on System-on-Chip for Real-Time Applications (IWSOC'03), 2003
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