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12th IEEE International Workshop on Rapid System Prototyping (RSP'01)
Prototyping of Efficient Hardware Algorithms for Data Compression in Future Communication Systems
Monterey, California
June 25-June 27
ISBN: 0-7695-1206-2
ASCII Text
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A. Mukherjee, N. Motgi, J. Becker, A. Friebe, C. Habermann, M. Glesner, "Prototyping of Efficient Hardware Algorithms for Data Compression in Future Communication Systems," Rapid System Prototyping, IEEE International Workshop on, pp. 0058, 12th IEEE International Workshop on Rapid System Prototyping (RSP'01), 2001.
 
 
BibTex
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@article{ 10.1109/IWRSP.2001.933839,
author = {A. Mukherjee and N. Motgi and J. Becker and A. Friebe and C. Habermann and M. Glesner},
title = {Prototyping of Efficient Hardware Algorithms for Data Compression in Future Communication Systems},
journal ={Rapid System Prototyping, IEEE International Workshop on},
volume = {0},
year = {2001},
isbn = {0-7695-1206-2},
pages = {0058},
doi = {http://doi.ieeecomputersociety.org/10.1109/IWRSP.2001.933839},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
x 
 
TY - CONF
JO - Rapid System Prototyping, IEEE International Workshop on
TI - Prototyping of Efficient Hardware Algorithms for Data Compression in Future Communication Systems
SN - 0-7695-1206-2
SP
EP
A1 - A. Mukherjee,
A1 - N. Motgi,
A1 - J. Becker,
A1 - A. Friebe,
A1 - C. Habermann,
A1 - M. Glesner,
PY - 2001
VL - 0
JA - Rapid System Prototyping, IEEE International Workshop on
ER -
 
A. Mukherjee, University of Central Florida
N. Motgi, University of Central Florida
J. Becker, Institute of Microelectronic Systems, Darmstadt University of Technology
A. Friebe, Institute of Microelectronic Systems, Darmstadt University of Technology
C. Habermann, Institute of Microelectronic Systems, Darmstadt University of Technology
M. Glesner, Institute of Microelectronic Systems, Darmstadt University of Technology
Abstract: Due to high bandwidth requirements up to 2 Mbits/sec in third generation mobile communication systems, efficient data compression approaches are necessary to reduce communication and storage costs. Recent VLSI technologies status promises complete System-on-Chip (SoC) solutions for both mobile and network based communication systems, including new compression algorithms based on Burrows-Wheeler transform (BWT). The most complex task of the BWT algorithm is its lexicographic sorting of n cyclic rotations of a given string of n characters. The paper discusses the feasibility and VLSI implementation of this scalable BWT architecture in simulating and prototyping its systolic highly utilized hardware structure with Virtex FPGAs.
Citation:
A. Mukherjee, N. Motgi, J. Becker, A. Friebe, C. Habermann, M. Glesner, "Prototyping of Efficient Hardware Algorithms for Data Compression in Future Communication Systems," rsp, pp.0058, 12th IEEE International Workshop on Rapid System Prototyping (RSP'01), 2001
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