A Loop Optimization Technique for Speculative Chip Multiprocessors

I
IWNAS
2006
2006 International Workshop on Networking, Architecture, and Storages (IWNAS'06)
Abstract - A Loop Optimization Technique for Speculative Chip Multiprocessors

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	Similar Articles Articles by Chao-Chin Wu Articles by Kuan-Chou Lai

2006 International Workshop on Networking, Architecture, and Storages (IWNAS'06)

Shenyang, China

August 01-August 03

ISBN: 0-7695-2651-9

	ASCII Text	x
	Chao-Chin Wu, Kuan-Chou Lai, "A Loop Optimization Technique for Speculative Chip Multiprocessors," Networking, Architecture, and Storages, International Workshop on, pp. 55-56, 2006 International Workshop on Networking, Architecture, and Storages (IWNAS'06), 2006.

	BibTex	x
	@article{ 10.1109/IWNAS.2006.9, author = {Chao-Chin Wu and Kuan-Chou Lai}, title = {A Loop Optimization Technique for Speculative Chip Multiprocessors}, journal ={Networking, Architecture, and Storages, International Workshop on}, volume = {0}, year = {2006}, isbn = {0-7695-2651-9}, pages = {55-56}, doi = {http://doi.ieeecomputersociety.org/10.1109/IWNAS.2006.9}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - Networking, Architecture, and Storages, International Workshop on TI - A Loop Optimization Technique for Speculative Chip Multiprocessors SN - 0-7695-2651-9 SP55 EP56 A1 - Chao-Chin Wu, A1 - Kuan-Chou Lai, PY - 2006 KW - null VL - 0 JA - Networking, Architecture, and Storages, International Workshop on ER -

Chao-Chin Wu, National Changhua University of Education, Taiwan

Kuan-Chou Lai, National Taichung University, Taichung, Taiwan

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/IWNAS.2006.9

According to the characteristics of chip multiprocessors, we propose a loop optimization technique to improve the system performance by reducing the occurrences of dependence violations.

Citation:

Chao-Chin Wu, Kuan-Chou Lai, "A Loop Optimization Technique for Speculative Chip Multiprocessors," iwnas, pp.55-56, 2006 International Workshop on Networking, Architecture, and Storages (IWNAS'06), 2006

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