In this paper we focus on the hardware acceleration of cryptographic algorithms by using instruction set extensions. Therefore, a holistic methodology for automated evaluation of instruction set extensions is presented. We propose a two-stage framework for analyzing the resource efficiency of extending an instruction set. With emphasis to elliptic curve cryptography, several instruction set extensions are implemented for a 32-bit RISC microprocessor and synthesized in a state of the art 65 nm low power standard cell CMOS technology. The achieved performance improvement is analyzed in respect to the hardware costs in terms of chip area and power consumption.