Efficient implementation of block ciphers is critical towards achieving both high security and high-speed processing. Numerous block ciphers have been proposed and implemented, using a wide and varied range of functional operations. Existing microprocessor architectures do not provide this broad range of support. However, the advent of intellectual property (IP) microprocessor cores presents the opportunity to augment existing datapaths and instruction sets to add acceleration modules. Therefore, we will present a hardware architecture that achieves efficient implementation of generalized Galois Field fixed field constant multiplication, a core operation of Rijndael, chosen by the National Institute of Standards and Technology (NIST) as the Advanced Encryption Standard (AES) Advanced Encryption Algorithm in October of 2000. A detailed discussion of the architecture will be provided and an analysis of system performance and resource utilization will be performed to demonstrate the efficiency versus other implementations.