Third International Conference on Information Technology: New Generations (ITNG'06)
ECC Hardware Coprocessors for 8-bit Systems and Power Consumption Considerations
Las Vegas, Nevada
April 10-April 12
ISBN: 0-7695-2497-4
In the group of public key algorithms, Elliptic Curve Cryptosystems (or ECC) are widely considered as the best compromise in terms of speed, memory requirement and security level. Recent researches have stressed the possibility of implementing ECC in low-end systems such as the nodes of a Wireless Sensor Network (WSN). The main constraints for such an application are implementation cost and power consumption. The nodes of a WNS are battery-equipped systems, and battery lifetime is a premium factor. In this paper we propose two novel coprocessor architectures: a 12 Kgate processor able to perform one kP operation (i.e. the ECC primitive) over the finite field GF(2^163) in 17.05 ms, consuming 1.1 mJ of energy, and a 18.5 Kgate coprocessor performing the same operation in 14.68 ms but consuming only 0.66 mJ. Both represent an advancement with respect to known literature comparable solutions.
Citation:
Guido Bertoni, Luca Breveglieri, Matteo Venturi, "ECC Hardware Coprocessors for 8-bit Systems and Power Consumption Considerations," itng, pp.573-574, Third International Conference on Information Technology: New Generations (ITNG'06), 2006