International Test Conference 2004 (ITC'04) Interconnect Delay Testing of Designs on Programmable Logic Devices Charlotte, NC, USA October 26-October 28 ISBN: 0-7803-8581-0
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/ITC.2004.99
Very thorough interconnect delay testing technique for designs implemented on programmable logic devices, such as FPGAs, is presented (application-dependent test). The presented technique achieves 1) 100% robust path delay coverage on all the paths in the design, 2) 100% transition fault coverage, and 3) 100% TARO coverage, transition to all reachable primary outputs. The required number of test configurations is two or four depending on the structure of the design. An algorithmic approach to generate the test vectors and configurations is presented.
Citation:
Mehdi Baradaran Tahoori, Subhasish Mitra, "Interconnect Delay Testing of Designs on Programmable Logic Devices," itc, pp.635-644, International Test Conference 2004 (ITC'04), 2004 Usage of this product signifies your acceptance of the Terms of Use. | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
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