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International Test Conference 2004 (ITC'04)
A Critical Path Selection Method for Delay Testing
Charlotte, NC, USA
October 26-October 28
ISBN: 0-7803-8581-0
ASCII Text
x 
 
Saravanan Padmanaban, Spyros Tragoudas, "A Critical Path Selection Method for Delay Testing," Test Conference, International, pp. 232-241, International Test Conference 2004 (ITC'04), 2004.
 
 
BibTex
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@article{ 10.1109/ITC.2004.8,
author = {Saravanan Padmanaban and Spyros Tragoudas},
title = {A Critical Path Selection Method for Delay Testing},
journal ={Test Conference, International},
volume = {0},
year = {2004},
issn = {1089-3539},
pages = {232-241},
doi = {http://doi.ieeecomputersociety.org/10.1109/ITC.2004.8},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
x 
 
TY - CONF
JO - Test Conference, International
TI - A Critical Path Selection Method for Delay Testing
SN - 1089-3539
SP232
EP241
A1 - Saravanan Padmanaban,
A1 - Spyros Tragoudas,
PY - 2004
KW - null
VL - 0
JA - Test Conference, International
ER -
 
Saravanan Padmanaban, Intel Corporation, Hillsboro, OR
Spyros Tragoudas, Southern Illinois University, Carbondale, IL
An approach for selecting critical paths along which testable path delay faults can exist is presented. The proposed method is particularly helpful on path intensive circuits. Critical paths are selected implicitly with the aid of a combination of decision diagrams. An implicit method to eliminate untestable faults along the selected paths is also presented. The effectiveness of the approach is demonstrated on path intensive ISCAS?85, ISCAS?89 and ITC?99 benchmarks.
Citation:
Saravanan Padmanaban, Spyros Tragoudas, "A Critical Path Selection Method for Delay Testing," itc, pp.232-241, International Test Conference 2004 (ITC'04), 2004
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