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International Test Conference 2004 (ITC'04)
Evaluation of the Quality of N-Detect Scan ATPG Patterns on a Processor
Charlotte, NC, USA
October 26-October 28
ISBN: 0-7803-8581-0
M. Enamul Amyeen, Intel Corporation, Hillsboro, OR
Srikanth Venkataraman, Intel Corporation, Hillsboro, OR
Ajay Ojha, Intel Corporation, Hillsboro, OR
Sangbong Lee, Intel Corporation, Hillsboro, OR
This paper evaluates N-detect scan ATPG patterns for their impact to test quality through simulation and fallout from production on a Pentium 4 processor using 90nm manufacturing technology. An incremental ATPG flow is used to generate N-detect test patterns. The generated patterns were applied in production with flows to determine overlap in fallout to different tests. The generated N-detect test patterns are then evaluated based on different metrics. The metrics include signal states, bridge fault coverage, stuck-at fault coverage and fault detection profile. The correlation between the different metrics is studied. Data from production fallout shows the effectiveness of N-detect tests. Further, the correlation between fallout data and the different metrics is analyzed.
Citation:
M. Enamul Amyeen, Srikanth Venkataraman, Ajay Ojha, Sangbong Lee, "Evaluation of the Quality of N-Detect Scan ATPG Patterns on a Processor," itc, pp.669-678, International Test Conference 2004 (ITC'04), 2004
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