International Test Conference 2004 (ITC'04) EFFICIENT PATTERN MAPPING FOR DETERMINISTIC LOGIC BIST Charlotte, NC, USA October 26-October 28 ISBN: 0-7803-8581-0
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/ITC.2004.66
Deterministic logic BIST (DLBIST) is an attractive test strategy, since it combines advantages of deterministic external testing and pseudo-random LBIST. Unfortunately, previously published DLBIST methods are unsuited for large ICs, since computing time and memory consumption of the DLBIST synthesis algorithms increase exponentially, or at least cubically, with the circuit size. In this paper, we propose a novel DLBIST synthesis procedure that has nearly linear complexity in terms of both computing time and memory consumption. The new algorithms are based on binary decision diagrams (BDDs). We demonstrate the efficiency of the new algorithms for industrial designs up to 2M gates.
Index Terms:
Logic BIST, BDDs
Citation:
Valentin Gherman, Hans-Joachim Wunderlich, Harald Vranken, Friedrich Hapke, Michael Wittke, Michael Garbers, "EFFICIENT PATTERN MAPPING FOR DETERMINISTIC LOGIC BIST," itc, pp.48-56, International Test Conference 2004 (ITC'04), 2004 Usage of this product signifies your acceptance of the Terms of Use. | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
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