International Test Conference 2004 (ITC'04) Charlotte, NC, USA October 26-October 28 ISBN: 0-7803-8581-0
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/ITC.2004.52
Nanometer technology have not only resulted in increasingly complex chips but is also exposing new defects and failure mechanisms during manufacturing that are challenging process and test engineers while they struggle to maintain high yield and low DPM. Silicon manufacturers are increasingly using structural test vectors to improve the process and consequently, reduce the defect rates. Structural vectors help detect defective parts and debug issues in an automated manner, which subsequently allows ramping up the yield for a given process fairly quickly. In addition, it reduces the number of escaped parts thereby guaranteeing lower DPM and fewer field returns. However, relying more on structural tests implies that the test set should be of the highest quality and may include vectors for fault models (in addition to stuckat faults) such as transition, path-delay, bridging, n-detect, in-line resistance, Iddq, etc., covering some of the new failure mechanisms.
Citation:
Nilanjan Mukherjee, "Cost of Test - Taking Control," itc, pp.1431, International Test Conference 2004 (ITC'04), 2004 Usage of this product signifies your acceptance of the Terms of Use. | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||