International Test Conference 2004 (ITC'04) Channel Masking Synthesis for Efficient On-Chip Test Compression Charlotte, NC, USA October 26-October 28 ISBN: 0-7803-8581-0
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/ITC.2004.48
The effectiveness of on-product Test Compression methods is degraded by the capture of unknown logic states ("X-states") by the scan elements. This paper describes a simple but cost-effective solution called channel masking that masks the X-states and allows test compression methods to be widely deployed on a variety of designs. It also discusses various aspects of the channel masking hardware and the synthesis and validation methodology to support its use in a typical design flow. Results are presented to show its effectiveness on some large industrial designs.
Citation:
Vivek Chickermane, Brian Foutz, Brion Keller, "Channel Masking Synthesis for Efficient On-Chip Test Compression," itc, pp.452-461, International Test Conference 2004 (ITC'04), 2004 Usage of this product signifies your acceptance of the Terms of Use. | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||