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International Test Conference 2004 (ITC'04)
Built-In Self-Test for System-on-Chip: A Case Study
Charlotte, NC, USA
October 26-October 28
ISBN: 0-7803-8581-0
Charles Stroud, Auburn University, Alabama USA
John Sunwoo, Auburn University, Alabama USA
Srinivas Garimella, Auburn University, Alabama USA
Jonathan Harris, Auburn University, Alabama USA
We describe the development of Built-In Self-Test (BIST) for a generic SoC consisting of a Field Programmable Gate Array (FPGA) core for application specific logic along with a processor and several memory cores. Our target device was the Atmel AT94K series System-on-Chip (SoC), also known as a Field Programmable System Level Integrated Circuit (FPSLIC). The original goal for this project was to develop BIST configurations to completely test the programmable logic and routing resources of the FPGA core and then to use the FPGA core to test the other cores. We found that the FPGA can provide only limited testing of the some memory cores and even less testing of the processor. The processor, on the other hand, provides more effective testing of some memory cores than the FPGA core. In addition, the ability of the processor to write the FPGA configuration memory provides an improved and more efficient method of testing the FPGA core. As a result, the processor core was the primary testing resource instead of the FPGA.
Citation:
Charles Stroud, John Sunwoo, Srinivas Garimella, Jonathan Harris, "Built-In Self-Test for System-on-Chip: A Case Study," itc, pp.837-846, International Test Conference 2004 (ITC'04), 2004
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