International Test Conference 2004 (ITC'04) AUTOMATIC LINEARITY (IP3) TEST WITH BUILT-IN PATTERN GENERATOR AND ANALYZER Charlotte, NC, USA October 26-October 28 ISBN: 0-7803-8581-0
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/ITC.2004.41
We present a Built-In Self-Test (BIST) approach based on direct digital synthesizer (DDS) for functionality testing of analog circuitry in mixed-signal systems. Of particular interest, and a main contribution of this paper, is the BIST-based hardware implementation and measurement of amplifier linearity (IP3) test using DDS. The approach described in this paper has been implemented in Verilog and synthesized into FPGAs where it was used for functional testing and compared to simulation results.
Citation:
Foster Dai, Charles Stroud, Dayu Yang, Shuying Qi, "AUTOMATIC LINEARITY (IP3) TEST WITH BUILT-IN PATTERN GENERATOR AND ANALYZER," itc, pp.271-280, International Test Conference 2004 (ITC'04), 2004 Usage of this product signifies your acceptance of the Terms of Use. | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||