An Optimized DFT and Test Pattern Generation Strategy for an Intel High Performance Microprocessor

I
ITC
2004
International Test Conference 2004 (ITC'04)
Abstract - An Optimized DFT and Test Pattern Generation Strategy for an Intel High Performance Microprocessor

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International Test Conference 2004 (ITC'04)

Charlotte, NC, USA

October 26-October 28

ISBN: 0-7803-8581-0

	ASCII Text	x
	David M. Wu, Mike Lin, Madhukar Reddy, Talal Jaber, Anil Sabbavarapu, Larry Thatcher, "An Optimized DFT and Test Pattern Generation Strategy for an Intel High Performance Microprocessor," Test Conference, International, pp. 38-47, International Test Conference 2004 (ITC'04), 2004.

	BibTex	x
	@article{ 10.1109/ITC.2004.30, author = {David M. Wu and Mike Lin and Madhukar Reddy and Talal Jaber and Anil Sabbavarapu and Larry Thatcher}, title = {An Optimized DFT and Test Pattern Generation Strategy for an Intel High Performance Microprocessor}, journal ={Test Conference, International}, volume = {0}, year = {2004}, issn = {1089-3539}, pages = {38-47}, doi = {http://doi.ieeecomputersociety.org/10.1109/ITC.2004.30}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - Test Conference, International TI - An Optimized DFT and Test Pattern Generation Strategy for an Intel High Performance Microprocessor SN - 1089-3539 SP38 EP47 A1 - David M. Wu, A1 - Mike Lin, A1 - Madhukar Reddy, A1 - Talal Jaber, A1 - Anil Sabbavarapu, A1 - Larry Thatcher, PY - 2004 KW - null VL - 0 JA - Test Conference, International ER -

David M. Wu, Intel Corporation

Mike Lin, Intel Corporation

Madhukar Reddy, Intel Corporation

Talal Jaber, Intel Corporation

Anil Sabbavarapu, Intel Corporation

Larry Thatcher, Intel Corporation

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/ITC.2004.30

This paper describes an optimized DFT architecture and its implementation strategy for an Intel high performance (>3 GHz) microprocessor. Major DFT features and ATPG techniques implemented are described and key results are presented to show the return-on-investments (ROI) in the high volumemanufacturing (HVM) test environments.

Citation:

David M. Wu, Mike Lin, Madhukar Reddy, Talal Jaber, Anil Sabbavarapu, Larry Thatcher, "An Optimized DFT and Test Pattern Generation Strategy for an Intel High Performance Microprocessor," itc, pp.38-47, International Test Conference 2004 (ITC'04), 2004

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