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International Test Conference 2004 (ITC'04)
X-Masking During Logic BIST and Its Impact on Defect Coverage
Charlotte, NC, USA
October 26-October 28
ISBN: 0-7803-8581-0
ASCII Text
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Yuyi Tang, Hans-Joachim Wunderlich, Harald Vranken, Friedrich Hapke, Michael Wittke, Piet Engelke, Ilia Polian, Bernd Becker, "X-Masking During Logic BIST and Its Impact on Defect Coverage," Test Conference, International, pp. 442-451, International Test Conference 2004 (ITC'04), 2004.
 
 
BibTex
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@article{ 10.1109/ITC.2004.207,
author = {Yuyi Tang and Hans-Joachim Wunderlich and Harald Vranken and Friedrich Hapke and Michael Wittke and Piet Engelke and Ilia Polian and Bernd Becker},
title = {X-Masking During Logic BIST and Its Impact on Defect Coverage},
journal ={Test Conference, International},
volume = {0},
year = {2004},
issn = {1089-3539},
pages = {442-451},
doi = {http://doi.ieeecomputersociety.org/10.1109/ITC.2004.207},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
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TY - CONF
JO - Test Conference, International
TI - X-Masking During Logic BIST and Its Impact on Defect Coverage
SN - 1089-3539
SP442
EP451
A1 - Yuyi Tang,
A1 - Hans-Joachim Wunderlich,
A1 - Harald Vranken,
A1 - Friedrich Hapke,
A1 - Michael Wittke,
A1 - Piet Engelke,
A1 - Ilia Polian,
A1 - Bernd Becker,
PY - 2004
KW - X-Masking
KW - Logic BIST
KW - Defect Coverage
KW - Resistive Bridging Faults
VL - 0
JA - Test Conference, International
ER -
 
Yuyi Tang, University of Stuttgart, Germany
Hans-Joachim Wunderlich, University of Stuttgart, Germany
Harald Vranken, Philips Research Laboratories, The Netherlands
Friedrich Hapke, Philips Semiconductors GmbH, Hamburg, Germany
Michael Wittke, Philips Semiconductors GmbH, Hamburg, Germany
Piet Engelke, Albert-Ludwigs-University, Germany
Ilia Polian, Albert-Ludwigs-University, Germany
Bernd Becker, Albert-Ludwigs-University, Germany
We present a technique for making a circuit ready for Logic BIST by masking unknown values at its outputs. In order to keep the silicon area cost low, some known bits in output responses are also allowed to be masked. These bits are selected based on a stuck-at n-detection based metric, such that the impact of masking on the defect coverage is minimal. An analysis based on a probabilistic model for resistive short defects indicates that the coverage loss for unmodeled defects is negligible for relatively low values of n.
Index Terms:
X-Masking, Logic BIST, Defect Coverage,Resistive Bridging Faults
Citation:
Yuyi Tang, Hans-Joachim Wunderlich, Harald Vranken, Friedrich Hapke, Michael Wittke, Piet Engelke, Ilia Polian, Bernd Becker, "X-Masking During Logic BIST and Its Impact on Defect Coverage," itc, pp.442-451, International Test Conference 2004 (ITC'04), 2004
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