At multiple Gb/s data rates, virtually all the communication architectures converge to serial where the clock timing is recovered at the receiver via various clock recovery schemes. While serial communication architectures and technologies were first developed and implemented in network centric communication systems that are characterized by relatively low volume, high cost, and high performance. However, continue pushing the same technologies to commodity applications such as personal computer (PC) will face severer challenges when cost and high volume constraints are imposed and the underline performance merit such as bit error rate (BER) is maintained at the same level of 10-12. The economical version of "Heisenberg Uncertainty Principle" for the relationship between cost and performance will be in contradicting with the simple technology scaling approach, unless: a.) new technologies are developed to meet low cost, high volume, high performance requirements; b) cost and performance requirements are relaxed. In this paper, we will focus on specific challenges faced in design and test multiple Gb/s ICs when cost, performance, and volume constraints are imposed simultaneously, and discuss plausible solutions.