For years at ITC we have debating about how to measure ASIC coverage. Over the years, though, we have never talked about measuring test coverage at the board or system level. As difficult as it is to get consensus about ASIC test coverage metrics, it is magnitudes more difficult to come up with a way to measure coverage at the board level. Board level testing must not only account for the functionality and performance of all the devices placed on the board, but it must also account for how the devices are assembled on to the board and how the devices interact with one another. Because of this level of complexity, the industry has avoided trying to come up with a "comprehensive" test coverage metric which accounts for all possible defects which may occur at a board or system level. Instead the industry has focused primarily on the assembly portion and "assumed" that the devices placed on the board were "known good". Even limiting the scope to assembly process, there is still a great deal of controversy in finding a metric to determine how well the product has been assembled.