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International Test Conference 2004 (ITC'04)
VirtualScan: A New Compressed Scan Technology for Test Cost Reduction
Charlotte, NC, USA
October 26-October 28
ISBN: 0-7803-8581-0
ASCII Text
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Laung-Terng Wang, Khader S. Abdel-Hafez, Shianling Wu, Xiaoqing Wen, Hiroshi Furukawa, Fei-Sheng Hsu, Shyh-Horng Lin, Sen-Wei Tsai, "VirtualScan: A New Compressed Scan Technology for Test Cost Reduction," Test Conference, International, pp. 916-925, International Test Conference 2004 (ITC'04), 2004.
 
 
BibTex
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@article{ 10.1109/ITC.2004.201,
author = {Laung-Terng Wang and Khader S. Abdel-Hafez and Shianling Wu and Xiaoqing Wen and Hiroshi Furukawa and Fei-Sheng Hsu and Shyh-Horng Lin and Sen-Wei Tsai},
title = {VirtualScan: A New Compressed Scan Technology for Test Cost Reduction},
journal ={Test Conference, International},
volume = {0},
year = {2004},
issn = {1089-3539},
pages = {916-925},
doi = {http://doi.ieeecomputersociety.org/10.1109/ITC.2004.201},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
x 
 
TY - CONF
JO - Test Conference, International
TI - VirtualScan: A New Compressed Scan Technology for Test Cost Reduction
SN - 1089-3539
SP916
EP925
A1 - Laung-Terng Wang,
A1 - Khader S. Abdel-Hafez,
A1 - Shianling Wu,
A1 - Xiaoqing Wen,
A1 - Hiroshi Furukawa,
A1 - Fei-Sheng Hsu,
A1 - Shyh-Horng Lin,
A1 - Sen-Wei Tsai,
PY - 2004
KW - null
VL - 0
JA - Test Conference, International
ER -
 
Laung-Terng Wang, SynTest Technologies, Inc., Sunnyvale , CA
Khader S. Abdel-Hafez, SynTest Technologies, Inc., Sunnyvale , CA
Shianling Wu, SynTest Technologies, Inc., Sunnyvale , CA
Xiaoqing Wen, Kyushu Institute of Technology, Japan
Hiroshi Furukawa, NEC Micro Systems, Ltd., Japan
Fei-Sheng Hsu, SynTest Technologies, Inc., Taiwan
Shyh-Horng Lin, SynTest Technologies, Inc., Taiwan
Sen-Wei Tsai, SynTest Technologies, Inc., Taiwan
This paper describes the VirtualScan technology for scan test cost reduction. Scan chains in a VirtualScan circuit are split into shorter ones and the gap between external scan ports and internal scan chains are bridged with a broadcaster and a compactor. Test patterns for a VirtualScan circuit are generated directly by one-pass VirtualScan ATPG, in which multi-capture clocking and maximum test compaction are supported. In addition, VirtualScan ATPG avoids unknown-value and aliasing effects algorithmically without adding any additional circuitry. The VirtualScan technology has achieved successful tape-outs of industrial chips and has been proven to be an efficient and easy-to-implement solution for scan test cost reduction.
Citation:
Laung-Terng Wang, Khader S. Abdel-Hafez, Shianling Wu, Xiaoqing Wen, Hiroshi Furukawa, Fei-Sheng Hsu, Shyh-Horng Lin, Sen-Wei Tsai, "VirtualScan: A New Compressed Scan Technology for Test Cost Reduction," itc, pp.916-925, International Test Conference 2004 (ITC'04), 2004
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