International Test Conference 2004 (ITC'04) A New Probing Technique for High-Speed/High-Density Printed Circuit Boards Charlotte, NC, USA October 26-October 28 ISBN: 0-7803-8581-0
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/ITC.2004.19
Bullock, in 1987 [Bull87] provided design-for-test (DFT) rules for probing printed circuit boards for In- Circuit testing. Many of these rules stand in good stead even today. However, recent technical advances in operational board speed are leading some to believe that In-Circuit testing cannot be performed on the high-speed sectors of boards soon to be designed. Due to the increasing usage of high-speed circuitry, there is worry in our industry that In-Circuit testing will be marginalized with no good substitute available. It is the purpose of this paper to show how access can be maintained, even on highly dense gigabit logic boards.
Citation:
Kenneth P. Parker, "A New Probing Technique for High-Speed/High-Density Printed Circuit Boards," itc, pp.365-374, International Test Conference 2004 (ITC'04), 2004 Usage of this product signifies your acceptance of the Terms of Use. | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
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