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International Test Conference 2004 (ITC'04)
Time/Area Tradeoffs in Testing Hierarchical SOCs With Hard Mega-Cores
Charlotte, NC, USA
October 26-October 28
ISBN: 0-7803-8581-0
Qiang Xu, McMaster University, Hamilton, ON
Nicola Nicolici, McMaster University, Hamilton, ON
Motivated by the presence of mega-cores in hierarchical systems-on-a-chip, this paper describes a new framework for the design space exploration of multi-level test access mechanisms. The proposed solution can rapidly analyze the tradeoffs between test application time and area overhead and it facilitates test data reuse for hard mega-cores.
Citation:
Qiang Xu, Nicola Nicolici, "Time/Area Tradeoffs in Testing Hierarchical SOCs With Hard Mega-Cores," itc, pp.1196-1202, International Test Conference 2004 (ITC'04), 2004
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