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International Test Conference 2004 (ITC'04)
Time/Area Tradeoffs in Testing Hierarchical SOCs With Hard Mega-Cores
Charlotte, NC, USA
October 26-October 28
ISBN: 0-7803-8581-0
ASCII Text
x 
 
Qiang Xu, Nicola Nicolici, "Time/Area Tradeoffs in Testing Hierarchical SOCs With Hard Mega-Cores," Test Conference, International, pp. 1196-1202, International Test Conference 2004 (ITC'04), 2004.
 
 
BibTex
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@article{ 10.1109/ITC.2004.189,
author = {Qiang Xu and Nicola Nicolici},
title = {Time/Area Tradeoffs in Testing Hierarchical SOCs With Hard Mega-Cores},
journal ={Test Conference, International},
volume = {0},
year = {2004},
issn = {1089-3539},
pages = {1196-1202},
doi = {http://doi.ieeecomputersociety.org/10.1109/ITC.2004.189},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
x 
 
TY - CONF
JO - Test Conference, International
TI - Time/Area Tradeoffs in Testing Hierarchical SOCs With Hard Mega-Cores
SN - 1089-3539
SP1196
EP1202
A1 - Qiang Xu,
A1 - Nicola Nicolici,
PY - 2004
KW - null
VL - 0
JA - Test Conference, International
ER -
 
Qiang Xu, McMaster University, Hamilton, ON
Nicola Nicolici, McMaster University, Hamilton, ON
Motivated by the presence of mega-cores in hierarchical systems-on-a-chip, this paper describes a new framework for the design space exploration of multi-level test access mechanisms. The proposed solution can rapidly analyze the tradeoffs between test application time and area overhead and it facilitates test data reuse for hard mega-cores.
Citation:
Qiang Xu, Nicola Nicolici, "Time/Area Tradeoffs in Testing Hierarchical SOCs With Hard Mega-Cores," itc, pp.1196-1202, International Test Conference 2004 (ITC'04), 2004
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