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International Test Conference 2004 (ITC'04)
Test Strategies For a 40Gbps Framer SoC
Charlotte, NC, USA
October 26-October 28
ISBN: 0-7803-8581-0
ASCII Text
x 
 
Hans T. Heineken, Jitendra B. Khare, "Test Strategies For a 40Gbps Framer SoC," Test Conference, International, pp. 758-763, International Test Conference 2004 (ITC'04), 2004.
 
 
BibTex
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@article{ 10.1109/ITC.2004.177,
author = {Hans T. Heineken and Jitendra B. Khare},
title = {Test Strategies For a 40Gbps Framer SoC},
journal ={Test Conference, International},
volume = {0},
year = {2004},
issn = {1089-3539},
pages = {758-763},
doi = {http://doi.ieeecomputersociety.org/10.1109/ITC.2004.177},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
x 
 
TY - CONF
JO - Test Conference, International
TI - Test Strategies For a 40Gbps Framer SoC
SN - 1089-3539
SP758
EP763
A1 - Hans T. Heineken,
A1 - Jitendra B. Khare,
PY - 2004
KW - null
VL - 0
JA - Test Conference, International
ER -
 
Hans T. Heineken, Ample Communications Inc. Sacramento, CA
Jitendra B. Khare, Ample Communications Inc. Sacramento, CA
This paper describes DFT/DFD/DFM strategies implemented on a 40Gbps framer chip. The device is a 1500 pin, over 10M gate SoC with multiple PLLs/DLLs and 2.5GHz IOs. Some novel techniques were required to ensure quality and manufacturability.
Citation:
Hans T. Heineken, Jitendra B. Khare, "Test Strategies For a 40Gbps Framer SoC," itc, pp.758-763, International Test Conference 2004 (ITC'04), 2004
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