International Test Conference 2004 (ITC'04) Test Scheduling for Network-on-Chip with BIST and Precedence Constraints Charlotte, NC, USA October 26-October 28 ISBN: 0-7803-8581-0
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/ITC.2004.176
Network-on-a-Chip (NoC) is becoming a promising paradigm of core-based system. In this paper, we propose a new method for test scheduling in NoC. The mehod is based on the use of a dedicated routing path for the rest of each core. We show that test scheduling under this approach is NP-complete and present and ILP model for solving small NoC instances. For NoCs with larger number of cores, we present an effecient heuristic. We then improve the heuristic by including BISTs and precedence constraints. Eperimental results for the ITC'02 SoC benchmarks show that the new method leads to substantial reduction on a test application time compared to previous work. The inclusion of BIST tests and precednce constraints provides a comprehensive solution for test scheduling in NoC.
Citation:
Chunsheng Liu, Hamid Sharif, Erika Cota, D.K. Pradhan, "Test Scheduling for Network-on-Chip with BIST and Precedence Constraints," itc, pp.1369-1378, International Test Conference 2004 (ITC'04), 2004 Usage of this product signifies your acceptance of the Terms of Use. | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||