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International Test Conference 2004 (ITC'04)
SIMULATION REQUIREMENTS FOR VECTORS IN ATE FORMATS
Charlotte, NC, USA
October 26-October 28
ISBN: 0-7803-8581-0
ASCII Text
x 
 
R Raghuraman, "SIMULATION REQUIREMENTS FOR VECTORS IN ATE FORMATS," Test Conference, International, pp. 1100-1107, International Test Conference 2004 (ITC'04), 2004.
 
 
BibTex
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@article{ 10.1109/ITC.2004.162,
author = {R Raghuraman},
title = {SIMULATION REQUIREMENTS FOR VECTORS IN ATE FORMATS},
journal ={Test Conference, International},
volume = {0},
year = {2004},
issn = {1089-3539},
pages = {1100-1107},
doi = {http://doi.ieeecomputersociety.org/10.1109/ITC.2004.162},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
x 
 
TY - CONF
JO - Test Conference, International
TI - SIMULATION REQUIREMENTS FOR VECTORS IN ATE FORMATS
SN - 1089-3539
SP1100
EP1107
A1 - R Raghuraman,
PY - 2004
KW - null
VL - 0
JA - Test Conference, International
ER -
 
R Raghuraman, Texas Instruments Ltd., Bangalore , India.
The simulation of test vectors in ATE formats is shown to facilitate diagnosis and prevention of failures at the ATE. This paper discusses the requirements for a simulationbased flow to validate the test vectors before being handed out to the ATE engineers. The experiences of running such a flow, developed based on this methodology, is also briefly described.
Citation:
R Raghuraman, "SIMULATION REQUIREMENTS FOR VECTORS IN ATE FORMATS," itc, pp.1100-1107, International Test Conference 2004 (ITC'04), 2004
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