There is a growing acceptance in the industry that with 0.13um processes and beyond, at-speed structural testing is the only viable methodology for achieving acceptable quality levels with acceptable yields. Fully embedded at-speed structural test approaches have been growing in use over the past seveal years. For embedded memories, fully embedded test approaches are now widespread in use. For random logic testing, three approaches are currently in use. The full scan ATPG methodology provides a fully external test approach. The more recent ATPG compression based methodolgies represent a hybrid approach consisting of some internal IP as well as reduced external scan test data. Finally the logic BIST methodology represents a fully embedded test approach requiring no external test data.