International Test Conference 2004 (ITC'04) Removing JTAG Bottlenecks in System Interconnect Test Charlotte, NC, USA October 26-October 28 ISBN: 0-7803-8581-0
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/ITC.2004.153
This paper presents a new methodology that removes JTAG bottlenecks in system interconnect test. JTAG test has a limitation by targeting only low-speed testing. But, the system interconnect test requires the test to be run at system clock speed through the cluster of the network and also needs to diagnose the skew and delay characteristics of the cluster. Resolving the synchronization issue between a highspeed pattern clock and TCK, the proposed technique enables high frequency interconnection testing, cluster testing, and delay testing. Experimental results with test vehicles show that the test technique can be used with complex interconnections including differential signal lines, AC coupling, latency, and optical signal interconnections.
Citation:
Hong-Shin Jun, Sung S. Chung, Sang H. Baeg, "Removing JTAG Bottlenecks in System Interconnect Test," itc, pp.173-180, International Test Conference 2004 (ITC'04), 2004 Usage of this product signifies your acceptance of the Terms of Use. | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||