Reducing Power Consumption in Memory ECC Checkers

I
ITC
2004
International Test Conference 2004 (ITC'04)
Abstract - Reducing Power Consumption in Memory ECC Checkers

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International Test Conference 2004 (ITC'04)

Charlotte, NC, USA

October 26-October 28

ISBN: 0-7803-8581-0

	ASCII Text	x
	Shalini Ghosh, Nur A. Touba, Sugato Basu, "Reducing Power Consumption in Memory ECC Checkers," Test Conference, International, pp. 1322-1331, International Test Conference 2004 (ITC'04), 2004.

	BibTex	x
	@article{ 10.1109/ITC.2004.152, author = {Shalini Ghosh and Nur A. Touba and Sugato Basu}, title = {Reducing Power Consumption in Memory ECC Checkers}, journal ={Test Conference, International}, volume = {0}, year = {2004}, issn = {1089-3539}, pages = {1322-1331}, doi = {http://doi.ieeecomputersociety.org/10.1109/ITC.2004.152}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - Test Conference, International TI - Reducing Power Consumption in Memory ECC Checkers SN - 1089-3539 SP1322 EP1331 A1 - Shalini Ghosh, A1 - Nur A. Touba, A1 - Sugato Basu, PY - 2004 KW - null VL - 0 JA - Test Conference, International ER -

Shalini Ghosh, Dept. of Electrical and Computer Engineering, University of Texas, Austin, TX

Nur A. Touba, Dept. of Electrical and Computer Engineering, University of Texas, Austin, TX

Sugato Basu, Dept. of Computer Sciences, University of Texas, Austin, TX

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/ITC.2004.152

In this paper, a method is proposed for reducing power consumption in memory ECC checker circuitry that provides SEC-DED. The degrees of freedom in selecting the parity check matrix are used to minimize power with little or no impact on area and delay. The power minimization method is applied to two popular SEC-DED codes: standard Hamming codes and odd-column-weight Hsiao codes. Experiments on actual memory traces of Spec and MediaBench benchmarks indicate that considering power in addition to area and delay when selecting the parity check matrix can result in power reductions of up to 27% for Hsiao codes and up to 41% for Hamming codes.

Citation:

Shalini Ghosh, Nur A. Touba, Sugato Basu, "Reducing Power Consumption in Memory ECC Checkers," itc, pp.1322-1331, International Test Conference 2004 (ITC'04), 2004

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