While design-for-test methods such as scan, ATPG, and memory BIST are now well established for ASIC products, their run-time for multi-million gate designs has become a problem. Too often, a tape-out is held up because pattern generation and verification are incomplete. This paper describes a holistic design-for-test approach which exploits both hierarchy and parallelism on every aspect of the DFT to minimize the run-time impact.