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International Test Conference 2004 (ITC'04)
Programmable At-Speed Array and Functional BIST for Embedded DRAM LSI
Charlotte, NC, USA
October 26-October 28
ISBN: 0-7803-8581-0
ASCII Text
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Masaji Kume, Katsutoshi Uehara, Minoru Itakura, Hideo Sawamoto, Toru Kobayashi, Masatoshi Hasegawa, Hideki Hayashi, "Programmable At-Speed Array and Functional BIST for Embedded DRAM LSI," Test Conference, International, pp. 988-996, International Test Conference 2004 (ITC'04), 2004.
 
 
BibTex
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@article{ 10.1109/ITC.2004.146,
author = {Masaji Kume and Katsutoshi Uehara and Minoru Itakura and Hideo Sawamoto and Toru Kobayashi and Masatoshi Hasegawa and Hideki Hayashi},
title = {Programmable At-Speed Array and Functional BIST for Embedded DRAM LSI},
journal ={Test Conference, International},
volume = {0},
year = {2004},
issn = {1089-3539},
pages = {988-996},
doi = {http://doi.ieeecomputersociety.org/10.1109/ITC.2004.146},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
x 
 
TY - CONF
JO - Test Conference, International
TI - Programmable At-Speed Array and Functional BIST for Embedded DRAM LSI
SN - 1089-3539
SP988
EP996
A1 - Masaji Kume,
A1 - Katsutoshi Uehara,
A1 - Minoru Itakura,
A1 - Hideo Sawamoto,
A1 - Toru Kobayashi,
A1 - Masatoshi Hasegawa,
A1 - Hideki Hayashi,
PY - 2004
KW - null
VL - 0
JA - Test Conference, International
ER -
 
Masaji Kume, Enterprise Server Division, Hitachi Ltd.
Katsutoshi Uehara, Enterprise Server Division, Hitachi Ltd.
Minoru Itakura, Enterprise Server Division, Hitachi Ltd.
Hideo Sawamoto, Enterprise Server Division, Hitachi Ltd.
Toru Kobayashi, Micro Device Division, Hitachi Ltd.
Masatoshi Hasegawa, Micro Device Division, Hitachi Ltd.
Hideki Hayashi, Hitachi ULSI Systems Co. Ltd.
A new approach to DFT (Design For Test) for an Embedded DRAM LSI is proposed in this paper. One powerful BIST engine is implemented on the LSI, which executes not only the array BIST for the DRAM and SRAM macros, but also functional BIST for the whole chip. It was implemented in an Embedded DRAM cache LSI which is presented together with measured results.
Citation:
Masaji Kume, Katsutoshi Uehara, Minoru Itakura, Hideo Sawamoto, Toru Kobayashi, Masatoshi Hasegawa, Hideki Hayashi, "Programmable At-Speed Array and Functional BIST for Embedded DRAM LSI," itc, pp.988-996, International Test Conference 2004 (ITC'04), 2004
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