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International Test Conference 2004 (ITC'04)
Post-Packaging Auto Repair Techniques for Fast Row Cycle Embedded DRAM
Charlotte, NC, USA
October 26-October 28
ISBN: 0-7803-8581-0
ASCII Text
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Osamu Wada, Toshimasa Namekawa, Hiroshi Ito, Atsushi Nakayama, Shuso Fujii, "Post-Packaging Auto Repair Techniques for Fast Row Cycle Embedded DRAM," Test Conference, International, pp. 1016-1023, International Test Conference 2004 (ITC'04), 2004.
 
 
BibTex
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@article{ 10.1109/ITC.2004.141,
author = {Osamu Wada and Toshimasa Namekawa and Hiroshi Ito and Atsushi Nakayama and Shuso Fujii},
title = {Post-Packaging Auto Repair Techniques for Fast Row Cycle Embedded DRAM},
journal ={Test Conference, International},
volume = {0},
year = {2004},
issn = {1089-3539},
pages = {1016-1023},
doi = {http://doi.ieeecomputersociety.org/10.1109/ITC.2004.141},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
x 
 
TY - CONF
JO - Test Conference, International
TI - Post-Packaging Auto Repair Techniques for Fast Row Cycle Embedded DRAM
SN - 1089-3539
SP1016
EP1023
A1 - Osamu Wada,
A1 - Toshimasa Namekawa,
A1 - Hiroshi Ito,
A1 - Atsushi Nakayama,
A1 - Shuso Fujii,
PY - 2004
KW - null
VL - 0
JA - Test Conference, International
ER -
 
Osamu Wada, Toshiba Corporation, Kawasaki, Japan
Toshimasa Namekawa, Toshiba Corporation, Kawasaki, Japan
Hiroshi Ito, Toshiba Corporation, Kawasaki, Japan
Atsushi Nakayama, Toshiba Corporation, Kawasaki, Japan
Shuso Fujii, Toshiba Corporation, Kawasaki, Japan
A post-packaging auto repair technique is implemented in a 36Mb embedded DRAM macro of 6ns cycle time. It consists of internal compare circuit, redundancy analyzer, and anti-fuses. The internal auto programming of anti-fuse fixes post-packaging failures.
Citation:
Osamu Wada, Toshimasa Namekawa, Hiroshi Ito, Atsushi Nakayama, Shuso Fujii, "Post-Packaging Auto Repair Techniques for Fast Row Cycle Embedded DRAM," itc, pp.1016-1023, International Test Conference 2004 (ITC'04), 2004
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