Analogue clusters on boards are tradionally tested in nass production using a bed-of-nails, often combined with functional system test. In general this approach requires additional board area to create test access, is not very flexible and is hard to re-use. On-chip methods provide a solution to overcome these drawbacks and are already widely used in the form of Boundary Scan for digital interconnections. For analogue interconnections also on-chip solutions are available. We analysed the coverage and application of two on-chip methods, IEEE std 1149.4 and the re-usage of existing Design-for-Testability for on-chip Mixed-Signal blocks. It was found that a reduction board test costs as well as test development time can be achieved by using, or rather re-using on-chip alternatives.