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International Test Conference 2004 (ITC'04)
Minimizing Power Consumption in Scan Testing: Pattern Generation and DFT Techniques
Charlotte, NC, USA
October 26-October 28
ISBN: 0-7803-8581-0
ASCII Text
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Kenneth M. Butler, Jayashree Saxena, Tony Fryars, Graham Hetherington, "Minimizing Power Consumption in Scan Testing: Pattern Generation and DFT Techniques," Test Conference, International, pp. 355-364, International Test Conference 2004 (ITC'04), 2004.
 
 
BibTex
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@article{ 10.1109/ITC.2004.120,
author = {Kenneth M. Butler and Jayashree Saxena and Tony Fryars and Graham Hetherington},
title = {Minimizing Power Consumption in Scan Testing: Pattern Generation and DFT Techniques},
journal ={Test Conference, International},
volume = {0},
year = {2004},
issn = {1089-3539},
pages = {355-364},
doi = {http://doi.ieeecomputersociety.org/10.1109/ITC.2004.120},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
x 
 
TY - CONF
JO - Test Conference, International
TI - Minimizing Power Consumption in Scan Testing: Pattern Generation and DFT Techniques
SN - 1089-3539
SP355
EP364
A1 - Kenneth M. Butler,
A1 - Jayashree Saxena,
A1 - Tony Fryars,
A1 - Graham Hetherington,
PY - 2004
KW - null
VL - 0
JA - Test Conference, International
ER -
 
Kenneth M. Butler, Texas Instruments Inc., Dallas
Jayashree Saxena, Texas Instruments Inc., Dallas
Tony Fryars, Texas Instruments Inc., Dallas
Graham Hetherington, Texas Instruments Inc., Dallas
It is a well-known phenomenon that test power consumption may exceed that of functional operation. ICs have been observed to fail at specified minimum operating voltages during structured at-speed testing while passing all other forms of test. Methods exist to reduce power without dramatically increasing pattern volume for a given coverage. We present case study information on ATPG- and DFT-based solutions for test power reduction.
Citation:
Kenneth M. Butler, Jayashree Saxena, Tony Fryars, Graham Hetherington, "Minimizing Power Consumption in Scan Testing: Pattern Generation and DFT Techniques," itc, pp.355-364, International Test Conference 2004 (ITC'04), 2004
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