loading...
 This Article 
   
 Share 
   
 Bibliographic References 
   
 Add to: 
 
Digg
Furl
Spurl
Blink
Simpy
Google
Del.icio.us
Y!MyWeb
 
 Search 
   
International Test Conference 2004 (ITC'04)
Charlotte, NC, USA
October 26-October 28
ISBN: 0-7803-8581-0
Takahiro J. Yamaguchi, Advantest Laboratories, Ltd., Sendai, Miyagi, Japan
Issues in design verification of high-speed serial I/O devices. The increasing data rate of high-speed I/O devices makes currently available measurement tools such as realtime oscilloscopes obsolete. Measuring jitter performance of prototyped physical layer ICs of 5 Gb/s will particularly become a critical problem using current-mainstream oscilloscope technology. Therefore, the architecture of oscilloscopes has to be changed from a high-speed ADCcentric to an equivalent-time (ET) sampling architecture in order to provide the capabilities necessary for measuring signal integrity at and above 5 Gb/s. It is well known that the ET sampling architecture has several disadvantages [1]:
Citation:
Takahiro J. Yamaguchi, "Loopback or not?," itc, pp.1434, International Test Conference 2004 (ITC'04), 2004
Usage of this product signifies your acceptance of the Terms of Use.