In this paper, subthreshold 1-bit full adder cells in sub-100 nm technologies are investigated. The analysis is performed using fourteen different full adder cells operating in subthreshold region by decomposing them into smaller blocks. Both individual blocks and the complete full adder cells are simulated. The study, which is carried out for 65nm and 90nm standard CMOS technologies, includes power, delay, and power delay product as functions of supply voltage, frequency, size, and technology. In addition, for both technologies, the minimum required supply voltage for different circuits, are determined.