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IEEE Computer Society Annual Symposium on VLSI (ISVLSI '07)
Performance Evaluation of Asynchronous Circuits with Choice Using Abstract Probabilistic Timed Petri Nets
Porto Alegre, Brazil
March 09-March 11
ISBN: 0-7695-2896-1
Mehrdad Najibi, Amirkabir University of Technology, Iran
Mahtab Niknahad, Amirkabir University of Technology, Iran
Hossein Pedram, Amirkabir University of Technology, Iran
A framework for evaluating the performance of asynchronous systems is presented. Due to the dependencies among highly concurrent events performance evaluation of asynchronous circuits is a challenging process. The presented performance model is a Probabilistic Timed Petri-Net (PTPN) with possible choice places to capture the conditional behavior of the system. The proposed framework takes advantage of both static and dynamic analysis to provide precisely enough results in an acceptable time. No data manipulation is done during the simulation phase of the performance evaluation method which leads to very fast simulation. Our proposed performance estimation scheme is faster than usual post-synthesis simulation by an order of 10, while the estimated performance resides in a boundary of 3% of the total imprecision.
Citation:
Mehrdad Najibi, Mahtab Niknahad, Hossein Pedram, "Performance Evaluation of Asynchronous Circuits with Choice Using Abstract Probabilistic Timed Petri Nets," isvlsi, pp.422-427, IEEE Computer Society Annual Symposium on VLSI (ISVLSI '07), 2007
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