Partial Product Reduction for Parallel Cubing

I
ISVLSI
2007
IEEE Computer Society Annual Symposium on VLSI (ISVLSI '07)
Abstract - Partial Product Reduction for Parallel Cubing

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IEEE Computer Society Annual Symposium on VLSI (ISVLSI '07)

Porto Alegre, Brazil

March 09-March 11

ISBN: 0-7695-2896-1

	ASCII Text	x
	James E. Stine, Jeff M. Blank, "Partial Product Reduction for Parallel Cubing," VLSI, IEEE Computer Society Annual Symposium on, pp. 337-342, IEEE Computer Society Annual Symposium on VLSI (ISVLSI '07), 2007.

	BibTex	x
	@article{ 10.1109/ISVLSI.2007.78, author = {James E. Stine and Jeff M. Blank}, title = {Partial Product Reduction for Parallel Cubing}, journal ={VLSI, IEEE Computer Society Annual Symposium on}, volume = {0}, year = {2007}, isbn = {0-7695-2896-1}, pages = {337-342}, doi = {http://doi.ieeecomputersociety.org/10.1109/ISVLSI.2007.78}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - VLSI, IEEE Computer Society Annual Symposium on TI - Partial Product Reduction for Parallel Cubing SN - 0-7695-2896-1 SP337 EP342 A1 - James E. Stine, A1 - Jeff M. Blank, PY - 2007 KW - null VL - 0 JA - VLSI, IEEE Computer Society Annual Symposium on ER -

James E. Stine, Oklahoma State University

Jeff M. Blank, Oklahoma State University

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/ISVLSI.2007.78

A new technique for computing the cube of an operand of any length is proposed, implemented, analyzed, and compared to existing techniques. The new proposed method is faster than previously proposed methods that compute the cube of an operand in parallel with the disadvantage that more counters are utilized to perform partial product reduction. Cubing circuits using the proposed techniques are implemented with several operand lengths and analyzed with regard to area consumption and latency. Results are shown for several designs in AMI C5N 0.6 ?m technology.

Citation:

James E. Stine, Jeff M. Blank, "Partial Product Reduction for Parallel Cubing," isvlsi, pp.337-342, IEEE Computer Society Annual Symposium on VLSI (ISVLSI '07), 2007

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