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IEEE Computer Society Annual Symposium on VLSI (ISVLSI '07)
Novel, High-Speed 16-Digit BCD Adders Conforming to IEEE 754r Format
Porto Alegre, Brazil
March 09-March 11
ISBN: 0-7695-2896-1
Sreehari Veeramachaneni, International Institute of Information Technology, India
M.Kirthi Krishna, International Institute of Information Technology, India
Lingamneni Avinash, International Institute of Information Technology, India
Reddy P Sreekanth, International Institute of Information Technology, India
M.B. Srinivas, International Institute of Information Technology, India
In view of increasing prominence of commercial, financial and internet-based applications that process data in decimal format, there is a renewed interest in providing hardware support to handle decimal data. In this paper, a new architecture for efficient 1-digit decimal addition of binary coded decimal (BCD) operands, which is the core of high speed multi-operand adders and floating decimal-point arithmetic, is proposed. Based on this 1-digit BCD adder, novel architectures for higher order (n-digit) BCD adders such as ripple carry adder and carry look-ahead adder are derived. The proposed circuits are compared (both qualitatively as well as quantitatively) with the existing circuits in literature and are shown to perform better. Simulation results show that the proposed 1-digit BCD adder achieves an improvement of 40% in delay. The 16-digit BCD lookahead adder using prefix logic is shown to perform at least 80% faster than the existing ripple carry one.
Citation:
Sreehari Veeramachaneni, M.Kirthi Krishna, Lingamneni Avinash, Reddy P Sreekanth, M.B. Srinivas, "Novel, High-Speed 16-Digit BCD Adders Conforming to IEEE 754r Format," isvlsi, pp.343-350, IEEE Computer Society Annual Symposium on VLSI (ISVLSI '07), 2007
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