Modeling Subthreshold Leakage Current in General Transistor Networks

I
ISVLSI
2007
IEEE Computer Society Annual Symposium on VLSI (ISVLSI '07)
Abstract - Modeling Subthreshold Leakage Current in General Transistor Networks

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	Similar Articles Articles by Paulo F Butzen Articles by Andre I. Reis Articles by Chris H. Kim Articles by Renato P. Ribas

IEEE Computer Society Annual Symposium on VLSI (ISVLSI '07)

Porto Alegre, Brazil

March 09-March 11

ISBN: 0-7695-2896-1

	ASCII Text	x
	Paulo F Butzen, Andre I. Reis, Chris H. Kim, Renato P. Ribas, "Modeling Subthreshold Leakage Current in General Transistor Networks," VLSI, IEEE Computer Society Annual Symposium on, pp. 512-513, IEEE Computer Society Annual Symposium on VLSI (ISVLSI '07), 2007.

	BibTex	x
	@article{ 10.1109/ISVLSI.2007.68, author = {Paulo F Butzen and Andre I. Reis and Chris H. Kim and Renato P. Ribas}, title = {Modeling Subthreshold Leakage Current in General Transistor Networks}, journal ={VLSI, IEEE Computer Society Annual Symposium on}, volume = {0}, year = {2007}, isbn = {0-7695-2896-1}, pages = {512-513}, doi = {http://doi.ieeecomputersociety.org/10.1109/ISVLSI.2007.68}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - VLSI, IEEE Computer Society Annual Symposium on TI - Modeling Subthreshold Leakage Current in General Transistor Networks SN - 0-7695-2896-1 SP512 EP513 A1 - Paulo F Butzen, A1 - Andre I. Reis, A1 - Chris H. Kim, A1 - Renato P. Ribas, PY - 2007 KW - null VL - 0 JA - VLSI, IEEE Computer Society Annual Symposium on ER -

Paulo F Butzen, UFRGS, Porto Alegre, Brazil

Andre I. Reis, Nangate Inc., Menlo Park, CA, USA

Chris H. Kim, University of Minnesota, Minneapolis, MN, USA

Renato P. Ribas, UFRGS, Porto Alegre, Brazil

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/ISVLSI.2007.68

An improved model for subthreshold leakage current in general transistor networks is proposed. Previous modeling, presented in the literature and originally focused on series-parallel topologies, has been extended to non-series-parallel device arrangements. The occurrence of on-switches in off-networks, ignored by previous works, is considered in the proposed static current analysis. This leakage model has been validated through electrical simulations, taking into account a 130nm process, with good correlation of the results.

Citation:

Paulo F Butzen, Andre I. Reis, Chris H. Kim, Renato P. Ribas, "Modeling Subthreshold Leakage Current in General Transistor Networks," isvlsi, pp.512-513, IEEE Computer Society Annual Symposium on VLSI (ISVLSI '07), 2007

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