loading...
 This Article 
   
 Share 
   
 Bibliographic References 
   
 Add to: 
 
Digg
Furl
Spurl
Blink
Simpy
Google
Del.icio.us
Y!MyWeb
 
 Search 
   
IEEE Computer Society Annual Symposium on VLSI (ISVLSI '07)
Investigating Simple Low Latency Reliable Multiported Register Files
Porto Alegre, Brazil
March 09-March 11
ISBN: 0-7695-2896-1
Andrew J. Ricketts, Pennsylvania State University
Madhu Mutyam, International Institute of Information Technology, India
N. Vijaykrishnan, Pennsylvania State University
Mary Jane Irwin, Pennsylvania State University
Multiport register files are a key component in the design and operation of high performance microprocessors. Due to the frequency of accesses of these register files per clock cycle errors manifested here can potentially spread rapidly. This can seriously compromise the validity of data and even system reliability. Errors may be caused from any number of possible sources including radiation induced soft errors, read or write errors, and permanent device errors. This work focuses on combating errors that affect a stored entry in a register file, but our techniques can often also detect and recover from many other potential sources of errors. Up to 4 bit errors are detectable with 6.25% storage overhead over an unprotected register file. The recovery for most types of errors requires in the order of a few nanoseconds and requires 4% less energy than a monolithic register file with comparable characteristics but no error protection.
Citation:
Andrew J. Ricketts, Madhu Mutyam, N. Vijaykrishnan, Mary Jane Irwin, "Investigating Simple Low Latency Reliable Multiported Register Files," isvlsi, pp.375-382, IEEE Computer Society Annual Symposium on VLSI (ISVLSI '07), 2007
Usage of this product signifies your acceptance of the Terms of Use.