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IEEE Computer Society Annual Symposium on VLSI (ISVLSI '07)
Hierarchical Concurrent Congestion and Wirelength Estimation in the Presence of IP Blocks
Porto Alegre, Brazil
March 09-March 11
ISBN: 0-7695-2896-1
Taraneh Taghavi, University of California, Los Angeles
Majid Sarrafzadeh, University of California, Los Angeles

With the increasing sophistication of circuits and specifically in the presence of IP blocks, new estimation methods are needed in the design flow of large-scale circuits. Up to now, a number of post-placement congestion estimation techniques in the presence of IP blocks have been presented.

We propose a novel stochastic pre-placement approach for concurrent congestion and wirelength estimation using the Rent?s exponent of the circuit. Our experiments illustrate that the proposed method can quickly and accurately estimate wirelength and congestion. Simulation results show that the average error of the proposed wirelength estimation technique is less than 7%. Moreover, it is shown that in presence of IP blocks using a congestion removal technique based on our congestion estimation method results in 12.8% decrease in overflow on average.

Citation:
Taraneh Taghavi, Majid Sarrafzadeh, "Hierarchical Concurrent Congestion and Wirelength Estimation in the Presence of IP Blocks," isvlsi, pp.213-218, IEEE Computer Society Annual Symposium on VLSI (ISVLSI '07), 2007
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