Recently, interest in prototyping asynchronous circuits on FPGAs has attracted the attention of a few. In the overall, prototyping asynchronous circuits on FPGAs followed two directions. The first direction advocates the implementation of pre-existing asynchronous techniques on current FPGAs while the second direction proposes novel architectures suitable for implementing asynchronous circuits. With the exception of a few attempts in the first direction [1, 2], bundled data approaches have been avoided altogether based on the argument that delays are difficult to predict in current FPGAs. Although this argument merits some consideration, one can tame to some degree the difficulties related to the delay problem by altering the conventional FPGA design flow. In this paper, we present a novel asynchronous technique based on a simplified micropipeline where all the control components are simple gates. Data flow through the pipeline is managed by a two-phase single wire handshaking protocol which requires that all stages in the pipeline have equal delays. The prototyping of this pipeline has been performed on a Xilinx Spartan XC2S300E-7FG456 chip using Xilinx ISE 8.2 design tools.