loading...
 This Article 
   
 Share 
   
 Bibliographic References 
   
 Add to: 
 
Digg
Furl
Spurl
Blink
Simpy
Google
Del.icio.us
Y!MyWeb
 
 Search 
   
IEEE Computer Society Annual Symposium on VLSI (ISVLSI '07)
Efficient VLSI Implementation of Memory-Based FFT Processors for DVB-T Applications
Porto Alegre, Brazil
March 09-March 11
ISBN: 0-7695-2896-1
Chin-Long Wey, National Central University, Jhongli, Taiwan
Wei-Chien Tang, National Central University, Jhongli, Taiwan
Shin-Yo Lin, National Central University, Jhongli, Taiwan
This paper presents a Radix-2 memory-based FFT Processors, namely, MBFFTP, with a memory size of N words for large N complex points, where each word contains 24 bits. The developed MBFFTP meets DVB-T standard and can handle both 2K and 8K modes in the same architecture. The processors have been designed and implemented in TSMC 0.18?m 1P6M process. Results show that simple MBFFTP achieves a maximum work frequency of 173MHz, where its core chip area is approximately 1.80 mm2 with a core power consumption of 40.80 mW at 55 MHz for 2K mode and 48.16 mW at 65 MHz for 8K mode.
Citation:
Chin-Long Wey, Wei-Chien Tang, Shin-Yo Lin, "Efficient VLSI Implementation of Memory-Based FFT Processors for DVB-T Applications," isvlsi, pp.98-106, IEEE Computer Society Annual Symposium on VLSI (ISVLSI '07), 2007
Usage of this product signifies your acceptance of the Terms of Use.