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IEEE Computer Society Annual Symposium on VLSI (ISVLSI '07)
Code-coverage Based Test Vector Generation for SystemC Designs
Porto Alegre, Brazil
March 09-March 11
ISBN: 0-7695-2896-1
Alair Dias Junior, Universidade Federal de Minas Gerais, Brazil
Diogenes Junior Cecilio da Silva, Universidade Federal de Minas Gerais, Brazil
This work presents a methodology for the automatic test vector generation for SystemC combinational designs based on code coverage analysis which is complementary to the functional testing. The method uses coverage information to generate test vectors capable of covering the portions of code not exercised by the Black-box testing. Vectors are generated using an instrumented code followed by a numerical optimization method. This approach does not suffer from restrictions related to symbolic execution such as defining array reference values and loop boundaries, as the code is really executed together with the optimization. We expect this combined methodology to achieve total code coverage of the design and reduce the fault of omission problem, undetectable by Structural testing alone.
Citation:
Alair Dias Junior, Diogenes Junior Cecilio da Silva, "Code-coverage Based Test Vector Generation for SystemC Designs," isvlsi, pp.198-206, IEEE Computer Society Annual Symposium on VLSI (ISVLSI '07), 2007
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