A comparison of low power architectures for digital delay measurement

I
ISVLSI
2007
IEEE Computer Society Annual Symposium on VLSI (ISVLSI '07)
Abstract - A comparison of low power architectures for digital delay measurement

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	Similar Articles Articles by Franco Martin-Pirchio Articles by Alfonso Chacon-Rodriguez Articles by Pedro Julian Articles by Pablo Mandolesi

IEEE Computer Society Annual Symposium on VLSI (ISVLSI '07)

Porto Alegre, Brazil

March 09-March 11

ISBN: 0-7695-2896-1

	ASCII Text	x
	Franco Martin-Pirchio, Alfonso Chacon-Rodriguez, Pedro Julian, Pablo Mandolesi, "A comparison of low power architectures for digital delay measurement," VLSI, IEEE Computer Society Annual Symposium on, pp. 498-499, IEEE Computer Society Annual Symposium on VLSI (ISVLSI '07), 2007.

	BibTex	x
	@article{ 10.1109/ISVLSI.2007.3, author = {Franco Martin-Pirchio and Alfonso Chacon-Rodriguez and Pedro Julian and Pablo Mandolesi}, title = {A comparison of low power architectures for digital delay measurement}, journal ={VLSI, IEEE Computer Society Annual Symposium on}, volume = {0}, year = {2007}, isbn = {0-7695-2896-1}, pages = {498-499}, doi = {http://doi.ieeecomputersociety.org/10.1109/ISVLSI.2007.3}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - VLSI, IEEE Computer Society Annual Symposium on TI - A comparison of low power architectures for digital delay measurement SN - 0-7695-2896-1 SP498 EP499 A1 - Franco Martin-Pirchio, A1 - Alfonso Chacon-Rodriguez, A1 - Pedro Julian, A1 - Pablo Mandolesi, PY - 2007 KW - null VL - 0 JA - VLSI, IEEE Computer Society Annual Symposium on ER -

Franco Martin-Pirchio, Universidad Nacional del Sur, Bahia Blanca, Argentina

Alfonso Chacon-Rodriguez, Instituto Tecnol?ogico de Costa Rica

Pedro Julian, Universidad Nacional del Sur, Bahia Blanca, Argentina

Pablo Mandolesi, Universidad Nacional del Sur, Bahia Blanca, Argentina

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/ISVLSI.2007.3

Two different versions of a method for the calculation of the delay between two digital signals with central frequencies in the range [20, 300] Hz are compared in terms of their power dissipation. Power dissipation simulations are run on both versions from their layout on a 0.35?m technology. The second version shows a cut of 37% in total dissipation under the same test conditions.

Citation:

Franco Martin-Pirchio, Alfonso Chacon-Rodriguez, Pedro Julian, Pablo Mandolesi, "A comparison of low power architectures for digital delay measurement," isvlsi, pp.498-499, IEEE Computer Society Annual Symposium on VLSI (ISVLSI '07), 2007

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