An Internal Partial Dynamic Reconfiguration Implementation of the JPEG Encoder for Low-Cost FPGAsb

I
ISVLSI
2007
IEEE Computer Society Annual Symposium on VLSI (ISVLSI '07)
Abstract - An Internal Partial Dynamic Reconfiguration Implementation of the JPEG Encoder for Low-Cost FPGAsb

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IEEE Computer Society Annual Symposium on VLSI (ISVLSI '07)

Porto Alegre, Brazil

March 09-March 11

ISBN: 0-7695-2896-1

	ASCII Text	x
	Antonino Tumeo, Matteo Monchiero, Gianluca Palermo, Fabrizio Ferrandi, Donatella Sciuto, "An Internal Partial Dynamic Reconfiguration Implementation of the JPEG Encoder for Low-Cost FPGAsb," VLSI, IEEE Computer Society Annual Symposium on, pp. 449-450, IEEE Computer Society Annual Symposium on VLSI (ISVLSI '07), 2007.

	BibTex	x
	@article{ 10.1109/ISVLSI.2007.25, author = {Antonino Tumeo and Matteo Monchiero and Gianluca Palermo and Fabrizio Ferrandi and Donatella Sciuto}, title = {An Internal Partial Dynamic Reconfiguration Implementation of the JPEG Encoder for Low-Cost FPGAsb}, journal ={VLSI, IEEE Computer Society Annual Symposium on}, volume = {0}, year = {2007}, isbn = {0-7695-2896-1}, pages = {449-450}, doi = {http://doi.ieeecomputersociety.org/10.1109/ISVLSI.2007.25}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - VLSI, IEEE Computer Society Annual Symposium on TI - An Internal Partial Dynamic Reconfiguration Implementation of the JPEG Encoder for Low-Cost FPGAsb SN - 0-7695-2896-1 SP449 EP450 A1 - Antonino Tumeo, A1 - Matteo Monchiero, A1 - Gianluca Palermo, A1 - Fabrizio Ferrandi, A1 - Donatella Sciuto, PY - 2007 KW - null VL - 0 JA - VLSI, IEEE Computer Society Annual Symposium on ER -

Antonino Tumeo, Politecnico di Milano, Italy

Matteo Monchiero, Politecnico di Milano, Italy

Gianluca Palermo, Politecnico di Milano, Italy

Fabrizio Ferrandi, Politecnico di Milano, Italy

Donatella Sciuto, Politecnico di Milano, Italy

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/ISVLSI.2007.25

This paper presents the design of a JPEG Encoder which exploits this feature. We propose a mixed HW/SW architecture, where most compute-intensive components of the application are mapped to application-specific HW cores. These cores can be alternated on the FPGA, by means of internal dynamic reconfiguration. Our purpose is to describe a real-world application of reconfigurable computing, illustrating how this approach allows to save area with negligible performance overhead.

Citation:

Antonino Tumeo, Matteo Monchiero, Gianluca Palermo, Fabrizio Ferrandi, Donatella Sciuto, "An Internal Partial Dynamic Reconfiguration Implementation of the JPEG Encoder for Low-Cost FPGAsb," isvlsi, pp.449-450, IEEE Computer Society Annual Symposium on VLSI (ISVLSI '07), 2007

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