An External Memory Circuit Validation Algorithm for Large VLSI Layouts

I
ISVLSI
2007
IEEE Computer Society Annual Symposium on VLSI (ISVLSI '07)
Abstract - An External Memory Circuit Validation Algorithm for Large VLSI Layouts

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IEEE Computer Society Annual Symposium on VLSI (ISVLSI '07)

Porto Alegre, Brazil

March 09-March 11

ISBN: 0-7695-2896-1

	ASCII Text	x
	Yokesh Kumar, Prosenjit Gupta, "An External Memory Circuit Validation Algorithm for Large VLSI Layouts," VLSI, IEEE Computer Society Annual Symposium on, pp. 510-511, IEEE Computer Society Annual Symposium on VLSI (ISVLSI '07), 2007.

	BibTex	x
	@article{ 10.1109/ISVLSI.2007.24, author = {Yokesh Kumar and Prosenjit Gupta}, title = {An External Memory Circuit Validation Algorithm for Large VLSI Layouts}, journal ={VLSI, IEEE Computer Society Annual Symposium on}, volume = {0}, year = {2007}, isbn = {0-7695-2896-1}, pages = {510-511}, doi = {http://doi.ieeecomputersociety.org/10.1109/ISVLSI.2007.24}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - VLSI, IEEE Computer Society Annual Symposium on TI - An External Memory Circuit Validation Algorithm for Large VLSI Layouts SN - 0-7695-2896-1 SP510 EP511 A1 - Yokesh Kumar, A1 - Prosenjit Gupta, PY - 2007 KW - null VL - 0 JA - VLSI, IEEE Computer Society Annual Symposium on ER -

Yokesh Kumar, International Institute of Information Technology, Hyderabad, India

Prosenjit Gupta, International Institute of Information Technology, Hyderabad, India

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/ISVLSI.2007.24

The circuit represented by a layout must be validated by comparing it to a schematic circuit to show that the functionality is same as intended. This done by testing for graph isomorphism between the layout and schematic circuit graphs. Circuits designed currently are so large that their corresponding data structures often exceed available main memory and thus, memory hierarchy issues like disk I/Os cannot be ignored. We present an I/O efficient procedure for testing graph isomorphism between circuit graphs. Our approach is based on the global partitioning and local matching phases along with deletion of matched vertices and we give an I/O efficient procedure for each of these phases.

Citation:

Yokesh Kumar, Prosenjit Gupta, "An External Memory Circuit Validation Algorithm for Large VLSI Layouts," isvlsi, pp.510-511, IEEE Computer Society Annual Symposium on VLSI (ISVLSI '07), 2007

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