In this paper, an analytical approach to path-based buffer insertion is presented. Using our formulation, various objective functions in buffer costs can be minimized. Previous path-based buffer insertion algorithms either employ inaccurate delay estimation leading to an infeasible solution or process each path independently that may not use the effects of shared nets in paths and therefore, cannot optimize buffer cost efficiently. Our approach was tested using ISCAS benchmarks. Experimental results show that our approach can satisfy timing constraints with a 46.69% reduction in the number of buffers. Reducing the number of the buffers can simultaneously reduce physical synthesis complexity as well as power consumption.