A Scalable Modeling Technique to Estimate Dynamic Thermal Design Power of Datapath Intensive Designs

I
ISVLSI
2007
IEEE Computer Society Annual Symposium on VLSI (ISVLSI '07)
Abstract - A Scalable Modeling Technique to Estimate Dynamic Thermal Design Power of Datapath Intensive Designs

	This Article
	Subscribers, please Login Purchase article: $19 PDF IEEE Xplore Subscribers RSS feed
	Share
	Email this Article to a friend
	Bibliographic References
	ASCII Text BibTex RefWorks Procite/RefMan
	Add to:
	Digg Furl Spurl Blink Simpy Google Del.icio.us Y!MyWeb
	Search
	Similar Articles Articles by Prashant Agrawal Articles by Srinivasa R. STG Articles by Ajit N. Oke Articles by Saurabh Vijay

IEEE Computer Society Annual Symposium on VLSI (ISVLSI '07)

Porto Alegre, Brazil

March 09-March 11

ISBN: 0-7695-2896-1

	ASCII Text	x
	Prashant Agrawal, Srinivasa R. STG, Ajit N. Oke, Saurabh Vijay, "A Scalable Modeling Technique to Estimate Dynamic Thermal Design Power of Datapath Intensive Designs," VLSI, IEEE Computer Society Annual Symposium on, pp. 389-394, IEEE Computer Society Annual Symposium on VLSI (ISVLSI '07), 2007.

	BibTex	x
	@article{ 10.1109/ISVLSI.2007.18, author = {Prashant Agrawal and Srinivasa R. STG and Ajit N. Oke and Saurabh Vijay}, title = {A Scalable Modeling Technique to Estimate Dynamic Thermal Design Power of Datapath Intensive Designs}, journal ={VLSI, IEEE Computer Society Annual Symposium on}, volume = {0}, year = {2007}, isbn = {0-7695-2896-1}, pages = {389-394}, doi = {http://doi.ieeecomputersociety.org/10.1109/ISVLSI.2007.18}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - VLSI, IEEE Computer Society Annual Symposium on TI - A Scalable Modeling Technique to Estimate Dynamic Thermal Design Power of Datapath Intensive Designs SN - 0-7695-2896-1 SP389 EP394 A1 - Prashant Agrawal, A1 - Srinivasa R. STG, A1 - Ajit N. Oke, A1 - Saurabh Vijay, PY - 2007 KW - null VL - 0 JA - VLSI, IEEE Computer Society Annual Symposium on ER -

Prashant Agrawal, CSE, Indian Institute of Technology

Srinivasa R. STG, MG-I, Intel Technology (I)(P) Ltd., India

Ajit N. Oke, MG-I, Intel Technology (I)(P) Ltd., India

Saurabh Vijay, MG-I, Intel Technology (I)(P) Ltd., India

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/ISVLSI.2007.18

In this paper, a power modeling approach for the estimation of dynamic power under Thermal Design Power (TDP1) for datapath intensive designs is proposed. Early estimation of TDP is crucial for the design of thermal and cooling solutions of a chip and for evaluating trade offs of different design alternatives. In this approach, the total switched capacitance and the dynamic power of each partition in the design is estimated as a function of bandwidth and effective toggle rate of the input data transactions. The model considers the impact of cross coupling capacitance on the total switching power besides scaling well for a proliferated design of the existing one. Results have been presented using a complex mobile chipset based on 90nm and having more than 15 million gates.

Citation:

Prashant Agrawal, Srinivasa R. STG, Ajit N. Oke, Saurabh Vijay, "A Scalable Modeling Technique to Estimate Dynamic Thermal Design Power of Datapath Intensive Designs," isvlsi, pp.389-394, IEEE Computer Society Annual Symposium on VLSI (ISVLSI '07), 2007

Peer Review Notice | Give Us Feedback

Usage of this product signifies your acceptance of the Terms of Use.