In nanometer scale CMOS parameter Itariations are a challenge for the design of high yield integrated circuits. This work presents an accurate and computer efficient methodology for statistical modeling of circuit blocks. The model handless co-variances between parameters and supports WD and D2D variations. Using numerical error propagation tecniques, it computes the statistical parameters that can be applied at higher level analysis tools, as for instance statistical timing analysis tools. Moreover; we develop a methodology to compute the sensitivity of the circuit output variance to each randon variable. This method can be employed by the designer or by an automatic tool in order to improve circuit yield.

The methodology for yield analysis proposed in this work is shown to be a solid alternative to traditional Monte Carlo analysis, reducing by orders of magnitude the number of electrical simulations required to characterize memory cells, logic gates and small combinational blocks at electric level. As a case study, we model the yield loss of a SRAM memory due to variability in access time considering variance in thresold voltage and channel width. The results obtained using the proposed model are compared with statistical results obtained by Monte Carlo simulation. A speedup of 70 x is achieved, with error less than 1%.