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IEEE Computer Society Annual Symposium on VLSI (ISVLSI '07)
Vector Processing Support for FPGA-Oriented High Performance Applications
Porto Alegre, Brazil
March 09-March 11
ISBN: 0-7695-2896-1
Hongyan Yang, New Jersey Institute of Technology
Shuai Wang, New Jersey Institute of Technology
Sotirios G. Ziavras, New Jersey Institute of Technology
Jie Hu, New Jersey Institute of Technology
In this paper, we propose and implement a vector processing system that includes two identical vector microprocessors embedded in two FPGA chips. Each vector microprocessor supports floating-point calculations and efficient sparse matrix operations. Dense matrix-matrix multiplication and sparse matrix-vector multiplication with benchmark matrices from various application domains were run on the system to evaluate its performance. The resulting calculation times are compared with those of a commercial PC to show the effectiveness of our approach.
Citation:
Hongyan Yang, Shuai Wang, Sotirios G. Ziavras, Jie Hu, "Vector Processing Support for FPGA-Oriented High Performance Applications," isvlsi, pp.447-448, IEEE Computer Society Annual Symposium on VLSI (ISVLSI '07), 2007
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